Quantifying the Impact of Process Variability on Microprocessor Behavior

Architects and chip makers are worried about the impact of increasing CMOS process variability. This variability can impact a processor’s performance and, depending on how aggressively the design is pushed, its reliability. We perform the first quantitative analysis of the impact of process variability on an RTL-level specification of a microprocessor core. For each pipeline stage, we compute the expected latency, as well as the standard deviation of this latency. We show that with even modest amounts of process variability, the impact on performance can be significant, and this impact can increase when using dynamic voltage scaling.